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Reel/Frame:	056725/0939			Pages:	7
		Recorded:	06/30/2021
Conveyance:	MERGER (SEE DOCUMENT FOR DETAILS).

Total properties: 31

Patent #:	7975164	Issue Dt:	07/05/2011	Application #:	12157081	Filing Dt:	06/06/2008
Publication #:	US20090307521	Pub Dt:	12/10/2009
Title:	DDR MEMORY CONTROLLER

Patent #:	8661285	Issue Dt:	02/25/2014	Application #:	13172740	Filing Dt:	06/29/2011
Publication #:	US20110258475	Pub Dt:	10/20/2011
Title:	DYNAMICALLY CALIBRATED DDR MEMORY CONTROLLER

Patent #:	NONE	Issue Dt:		Application #:	13797200	Filing Dt:	03/12/2013
Publication #:	US20140281662	Pub Dt:	09/18/2014
Title:	DYNAMICALLY ADAPTIVE BIT-LEVELING FOR DATA INTERFACES

Patent #:	8843778	Issue Dt:	09/23/2014	Application #:	14023630	Filing Dt:	09/11/2013
Publication #:	US20140013149	Pub Dt:	01/09/2014
Title:	Dynamically Calibrated DDR Memory Controller

Patent #:	8990607	Issue Dt:	03/24/2015	Application #:	14081806	Filing Dt:	11/15/2013
Publication #:	US20140075236	Pub Dt:	03/13/2014
Title:	MEMORY INTERFACE CIRCUITS INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES

Patent #:	9021293	Issue Dt:	04/28/2015	Application #:	14081897	Filing Dt:	11/15/2013
Publication #:	US20140075146	Pub Dt:	03/13/2014
Title:	METHODS FOR OPERATING A MEMORY INTERFACE CIRCUIT INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES

Patent #:	9075543	Issue Dt:	07/07/2015	Application #:	14152807	Filing Dt:	01/10/2014
Publication #:	US20140129791	Pub Dt:	05/08/2014
Title:	Method of Application Memory Preservation for Dynamic Calibration of Memory Interfaces

Patent #:	9081516	Issue Dt:	07/14/2015	Application #:	14152902	Filing Dt:	01/10/2014
Publication #:	US20140129870	Pub Dt:	05/08/2014
Title:	Application Memory Preservation for Dynamic Calibration of Memory Interfaces

Patent #:	8947140	Issue Dt:	02/03/2015	Application #:	14205208	Filing Dt:	03/11/2014
Publication #:	US20140266347	Pub Dt:	09/18/2014
Title:	CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION

Patent #:	8941422	Issue Dt:	01/27/2015	Application #:	14205225	Filing Dt:	03/11/2014
Publication #:	US20140266348	Pub Dt:	09/18/2014
Title:	METHOD FOR OPERATING A DATA INTERFACE CIRCUIT WHERE A CALIBRATION CONTROLLER CONTROLS BOTH A MISSION PATH AND A REFERENCE PATH

Patent #:	9100027	Issue Dt:	08/04/2015	Application #:	14205239	Filing Dt:	03/11/2014
Publication #:	US20140281198	Pub Dt:	09/18/2014
Title:	DATA INTERFACE CIRCUIT FOR CAPTURING RECEIVED DATA BITS INCLUDING CONTINUOUS CALIBRATION

Patent #:	8941423	Issue Dt:	01/27/2015	Application #:	14205254	Filing Dt:	03/11/2014
Publication #:	US20140266349	Pub Dt:	09/18/2014
Title:	METHOD FOR OPERATING A CIRCUIT INCLUDING A TIMING CALIBRATION FUNCTION

Patent #:	9300443	Issue Dt:	03/29/2016	Application #:	14273416	Filing Dt:	05/08/2014
Publication #:	US20140281666	Pub Dt:	09/18/2014
Title:	METHODS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING

Patent #:	NONE	Issue Dt:		Application #:	14273438	Filing Dt:	05/08/2014
Publication #:	US20150006980	Pub Dt:	01/01/2015
Title:	CIRCUITS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY SWEEP SAMPLING WITH AUTOMATIC JITTER AVOIDANCE

Patent #:	NONE	Issue Dt:		Application #:	14273455	Filing Dt:	05/08/2014
Publication #:	US20140372787	Pub Dt:	12/18/2014
Title:	METHODS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY SWEEP SAMPLING WITH AUTOMATIC JITTER AVOIDANCE

Patent #:	9552853	Issue Dt:	01/24/2017	Application #:	14752903	Filing Dt:	06/27/2015
Publication #:	US20150302905	Pub Dt:	10/22/2015
Title:	METHODS FOR CALIBRATING A READ DATA PATH FOR A MEMORY INTERFACE

Patent #:	9425778	Issue Dt:	08/23/2016	Application #:	14850792	Filing Dt:	09/10/2015
Publication #:	US20160006423	Pub Dt:	01/07/2016
Title:	CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

Patent #:	9431091	Issue Dt:	08/30/2016	Application #:	14882226	Filing Dt:	10/13/2015
Publication #:	US20160035409	Pub Dt:	02/04/2016
Title:	Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR Memory Controllers

Patent #:	9584309	Issue Dt:	02/28/2017	Application #:	15078939	Filing Dt:	03/23/2016
Publication #:	US20160254903	Pub Dt:	09/01/2016
Title:	CIRCUIT FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING

Patent #:	9898433	Issue Dt:	02/20/2018	Application #:	15237473	Filing Dt:	08/15/2016
Publication #:	US20170075837	Pub Dt:	03/16/2017
Title:	CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

Patent #:	9805784	Issue Dt:	10/31/2017	Application #:	15249188	Filing Dt:	08/26/2016
Publication #:	US20160365135	Pub Dt:	12/15/2016
Title:	Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR Memory Controllers

Patent #:	10229729	Issue Dt:	03/12/2019	Application #:	15722209	Filing Dt:	10/02/2017
Publication #:	US20180033477	Pub Dt:	02/01/2018
Title:	METHOD FOR CALIBRATING CAPTURING READ DATA IN A READ DATA PATH FOR A DDR MEMORY INTERFACE CIRCUIT

Patent #:	NONE	Issue Dt:		Application #:	15853568	Filing Dt:	12/22/2017
Publication #:	US20180121382	Pub Dt:	05/03/2018
Title:	CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

Patent #:	10032502	Issue Dt:	07/24/2018	Application #:	15926902	Filing Dt:	03/20/2018
Publication #:	US20180211699	Pub Dt:	07/26/2018
Title:	METHOD FOR CALIBRATING CAPTURING READ DATA IN A READ DATA PATH FOR A DDR MEMORY INTERFACE CIRCUIT

Patent #:	10242730	Issue Dt:	03/26/2019	Application #:	15996365	Filing Dt:	06/01/2018
Publication #:	US20180277195	Pub Dt:	09/27/2018
Title:	DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

Patent #:	10269408	Issue Dt:	04/23/2019	Application #:	16049693	Filing Dt:	07/30/2018
Publication #:	US20180336942	Pub Dt:	11/22/2018
Title:	DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

Patent #:	NONE	Issue Dt:		Application #:	16254436	Filing Dt:	01/22/2019
Publication #:	US20190286591	Pub Dt:	09/19/2019
Title:	CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

Patent #:	10586585	Issue Dt:	03/10/2020	Application #:	16296025	Filing Dt:	03/07/2019
Publication #:	US20190206479	Pub Dt:	07/04/2019
Title:	DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

Patent #:	10734061	Issue Dt:	08/04/2020	Application #:	16584600	Filing Dt:	09/26/2019
Publication #:	US20200020381	Pub Dt:	01/16/2020
Title:	DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

Patent #:	11348632	Issue Dt:	05/31/2022	Application #:	16909871	Filing Dt:	06/23/2020
Publication #:	US20200321044	Pub Dt:	10/08/2020
Title:	DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

Patent #:	11334509	Issue Dt:	05/17/2022	Application #:	17074403	Filing Dt:	10/19/2020
Publication #:	US20210209043	Pub Dt:	07/08/2021
Title:	CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

Assignor

UNIQUIFY IP COMPANY, LLC

Exec Dt:

06/30/2021

Assignee

UNIQUIFY, INC.

2030 FORTUNE DRIVE, SUITE 200

SAN JOSE, CALIFORNIA 95131

Correspondence name and address
	LINDA A. SALERA, SENIOR PARALEGAL
	ONE FEDERAL STREET
	C/O MORGAN, LEWIS & BOCKIUS LLP
	BOSTON, MA 02110

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