Patent Assignment Details
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| Reel/Frame: | 051287/0941 | |
| Pages: | 5 |
| | Recorded: | 12/16/2019 | | |
| Attorney Dkt #: | 1242236-0913-286 US |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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16294055
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Filing Dt:
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03/06/2019
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Publication #:
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Pub Dt:
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03/26/2020
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Title:
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DESIGN METHOD FOR SCAN TEST CIRCUIT, DESIGN PROGRAM FOR SCAN TEST CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
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Assignees
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, JAPAN |
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| 1-1, SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, JAPAN 105-0023 |
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Correspondence name and address
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WHITE & CASE LLP
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701 THIRTEENTH STREET, NW
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WASHINGTON, DC 20005-3807
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