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Reel/Frame:015483/0947   Pages: 5
Recorded: 07/01/2004
Attorney Dkt #:20003-013
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 63
1
Patent #:
Issue Dt:
11/23/2004
Application #:
09969841
Filing Dt:
10/02/2001
Publication #:
Pub Dt:
04/10/2003
Title:
NONVOLATILE MEMORY STRUCTURES AND FABRICATION METHODS
2
Patent #:
Issue Dt:
08/24/2004
Application #:
09976331
Filing Dt:
10/12/2001
Publication #:
Pub Dt:
05/01/2003
Title:
DETERMINING AN ENDPOINT IN A POLISHING PROCESS
3
Patent #:
Issue Dt:
08/17/2004
Application #:
10020452
Filing Dt:
12/14/2001
Publication #:
Pub Dt:
06/19/2003
Title:
MULTIPLE PHOTOLITHOGRAPHIC EXPOSURES WITH DIFFERENT CLEAR PATTERNS
4
Patent #:
Issue Dt:
04/11/2006
Application #:
10033114
Filing Dt:
10/22/2001
Publication #:
Pub Dt:
04/24/2003
Title:
REDUCED THICKNESS VARIATION IN A MATERIAL LAYER DEPOSITED IN NORROW AND WIDE INTEGRATED CIRCUIT TRENCHES
5
Patent #:
Issue Dt:
01/10/2006
Application #:
10056154
Filing Dt:
01/23/2002
Publication #:
Pub Dt:
08/07/2003
Title:
COBALT SILICIDE FABRICATION USING PROTECTIVE TITANIUM
6
Patent #:
Issue Dt:
06/22/2004
Application #:
10058174
Filing Dt:
01/25/2002
Publication #:
Pub Dt:
07/31/2003
Title:
MULTIPLE PHOTOLITHOGRAPHIC EXPOSURES WITH DIFFERENT NON-CLEAR PATTERNS
7
Patent #:
NONE
Issue Dt:
Application #:
10071689
Filing Dt:
02/08/2002
Publication #:
Pub Dt:
08/14/2003
Title:
Floating gate nitridation
8
Patent #:
NONE
Issue Dt:
Application #:
10080468
Filing Dt:
02/22/2002
Publication #:
Pub Dt:
08/28/2003
Title:
HDP CVD process for void-free gap fill of a high aspect ratio trench
9
Patent #:
Issue Dt:
09/07/2004
Application #:
10109212
Filing Dt:
03/27/2002
Publication #:
Pub Dt:
01/02/2003
Title:
THIN TITANIUM NITRIDE LAYERS USED IN CONJUNCTION WITH TUNGSTEN
10
Patent #:
Issue Dt:
08/17/2004
Application #:
10136498
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
09/05/2002
Title:
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT WITH A TRANSISTOR ELECTRODE
11
Patent #:
NONE
Issue Dt:
Application #:
10184661
Filing Dt:
06/26/2002
Publication #:
Pub Dt:
08/14/2003
Title:
Floating gate nitridation
12
Patent #:
Issue Dt:
09/21/2004
Application #:
10198825
Filing Dt:
07/18/2002
Publication #:
Pub Dt:
01/22/2004
Title:
TWO STAGE ETCHING OF SILICON NITRIDE TO FORM A NITRIDE SPACER
13
Patent #:
Issue Dt:
11/09/2004
Application #:
10200443
Filing Dt:
07/22/2002
Publication #:
Pub Dt:
04/10/2003
Title:
NONVOLATILE MEMORY STRUCTURES AND FABRICATION METHODS
14
Patent #:
Issue Dt:
05/25/2004
Application #:
10202992
Filing Dt:
07/25/2002
Publication #:
Pub Dt:
01/29/2004
Title:
METHOD OF ETCHING A DIELECTRIC MATERIAL IN THE PRESENCE OF POLYSILICON
15
Patent #:
Issue Dt:
10/17/2006
Application #:
10243379
Filing Dt:
09/12/2002
Publication #:
Pub Dt:
03/18/2004
Title:
ATOMIC LAYER DEPOSITION OF INTERPOLY OXIDES IN A NON-VOLATILE MEMORY DEVICE
16
Patent #:
Issue Dt:
05/17/2005
Application #:
10243791
Filing Dt:
09/12/2002
Publication #:
Pub Dt:
03/18/2004
Title:
METHOD FOR FORMING A PROTECTIVE BUFFER LAYER FOR HIGH TEMPERATURE OXIDE PROCESSING
17
Patent #:
Issue Dt:
02/28/2006
Application #:
10252143
Filing Dt:
09/19/2002
Publication #:
Pub Dt:
03/25/2004
Title:
NONVOLATILE MEMORY CELL WITH A FLOATING GATE AT LEAST PARTIALLY LOCATED IN A TRENCH IN A SEMICONDUCTOR SUBSTRATE
18
Patent #:
Issue Dt:
04/05/2005
Application #:
10253738
Filing Dt:
09/23/2002
Publication #:
Pub Dt:
01/23/2003
Title:
POLISHING SYSTEM INCLUDING A HYDROSTATIC FLUID BEARING SUPPORT
19
Patent #:
Issue Dt:
06/01/2004
Application #:
10262785
Filing Dt:
10/01/2002
Publication #:
Pub Dt:
04/01/2004
Title:
FLOATING GATE MEMORY FABRICATION METHODS COMPRISING A FIELD DIELECTRIC ETCH WITH A HORIZONTAL ETCH COMPONENT
20
Patent #:
NONE
Issue Dt:
Application #:
10266378
Filing Dt:
10/07/2002
Publication #:
Pub Dt:
04/08/2004
Title:
Floating gate memory structures and fabrication methods
21
Patent #:
Issue Dt:
12/28/2004
Application #:
10300231
Filing Dt:
11/19/2002
Publication #:
Pub Dt:
04/17/2003
Title:
FORMING CONDUCTIVE LAYERS ON INSULATORS BY PHYSICAL VAPOR DEPOSITION
22
Patent #:
Issue Dt:
09/07/2004
Application #:
10305464
Filing Dt:
11/26/2002
Publication #:
Pub Dt:
05/27/2004
Title:
TRENCH ISOLATION WITHOUT GROOVING
23
Patent #:
Issue Dt:
04/19/2005
Application #:
10306397
Filing Dt:
11/27/2002
Publication #:
Pub Dt:
05/27/2004
Title:
PHOTOLITHOGRAPHY METHOD INCLUDING A DOUBLE EXPOSURE/DOUBLE BAKE
24
Patent #:
Issue Dt:
10/18/2005
Application #:
10309473
Filing Dt:
12/03/2002
Publication #:
Pub Dt:
06/03/2004
Title:
COMPARISON OF CHEMICAL-MECHANICAL POLISHING PROCESSES
25
Patent #:
Issue Dt:
08/02/2005
Application #:
10373917
Filing Dt:
02/24/2003
Publication #:
Pub Dt:
08/26/2004
Title:
METHOD OF MAKING A SILICON NITRIDE FILM THAT IS TRANSMISSIVE TO ULTRAVIOLET LIGHT
26
Patent #:
Issue Dt:
02/07/2006
Application #:
10393202
Filing Dt:
03/19/2003
Publication #:
Pub Dt:
09/23/2004
Title:
FABRICATION OF INTEGRATED CIRCUIT ELEMENTS IN STRUCTURES WITH PROTRUDING FEATURES
27
Patent #:
Issue Dt:
11/08/2005
Application #:
10393212
Filing Dt:
03/19/2003
Publication #:
Pub Dt:
09/23/2004
Title:
NONVOLATILE MEMORIES AND METHODS OF FABRICATION
28
Patent #:
Issue Dt:
09/07/2004
Application #:
10402698
Filing Dt:
03/28/2003
Publication #:
Pub Dt:
09/30/2004
Title:
NONVOLATILE MEMORY WITH PEDESTALS
29
Patent #:
NONE
Issue Dt:
Application #:
10402745
Filing Dt:
03/28/2003
Publication #:
Pub Dt:
09/30/2004
Title:
Method for etching a titanium-containing layer prior to etching an aluminum layer in a metal stack
30
Patent #:
Issue Dt:
05/17/2005
Application #:
10411813
Filing Dt:
04/16/2015
Publication #:
Pub Dt:
10/14/2004
Title:
NONVOLATILE MEMORIES WITH A FLOATING GATE HAVING AN UPWARD PROTRUSION
31
Patent #:
Issue Dt:
02/01/2005
Application #:
10423162
Filing Dt:
04/24/2003
Publication #:
Pub Dt:
03/18/2004
Title:
METHOD FOR FORMING A PROTECTIVE BUFFER LAYER FOR HIGH TEMPERATURE OXIDE PROCESSING
32
Patent #:
Issue Dt:
06/29/2004
Application #:
10434262
Filing Dt:
05/07/2003
Publication #:
Pub Dt:
11/06/2003
Title:
NONVOLATILE MEMORY STRUCTURES AND FABRICATION METHODS
33
Patent #:
Issue Dt:
12/13/2005
Application #:
10440005
Filing Dt:
05/16/2003
Publication #:
Pub Dt:
11/18/2004
Title:
FABRICATION OF DIELECTRIC ON A GATE SURFACE TO INSULATE THE GATE FROM ANOTHER ELEMENT OF AN INTEGRATED CIRCUIT
34
Patent #:
Issue Dt:
06/07/2005
Application #:
10440466
Filing Dt:
05/16/2003
Publication #:
Pub Dt:
02/10/2005
Title:
FABRICATION OF CONDUCTIVE GATES FOR NONVOLATILE MEMORIES FROM LAYERS WITH PROTRUDING PORTIONS
35
Patent #:
Issue Dt:
05/08/2007
Application #:
10440500
Filing Dt:
05/16/2003
Publication #:
Pub Dt:
11/18/2004
Title:
METHODS OF FABRICATING INTEGRATED CIRCUITS WITH OPENINGS THAT ALLOW ELECTRICAL CONTACT TO CONDUCTIVE FEATURES HAVING SELF-ALIGNED EDGES
36
Patent #:
Issue Dt:
01/25/2005
Application #:
10440508
Filing Dt:
05/16/2003
Publication #:
Pub Dt:
11/18/2004
Title:
FABRICATION OF GATE DIELECTRIC IN NONVOLATILE MEMORIES HAVING SELECT, FLOATING AND CONTROL GATES
37
Patent #:
Issue Dt:
07/04/2006
Application #:
10442759
Filing Dt:
05/20/2003
Publication #:
Pub Dt:
11/25/2004
Title:
METHODS FOR IMPROVING QUALITY OF SEMICONDUCTOR OXIDE COMPOSITION FORMED FROM HALOGEN-CONTAINING PRECURSOR
38
Patent #:
Issue Dt:
06/13/2006
Application #:
10631452
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
FABRICATION OF DIELECTRIC FOR A NONVOLATILE MEMORY CELL HAVING MULTIPLE FLOATING GATES
39
Patent #:
Issue Dt:
11/08/2005
Application #:
10631552
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
09/23/2004
Title:
NONVOLATILE MEMORIES AND METHODS OF FABRICATION
40
Patent #:
Issue Dt:
01/30/2007
Application #:
10631941
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
NONVOLATILE MEMORY CELL WITH MULTIPLE FLOATING GATES FORMED AFTER THE SELECT GATE
41
Patent #:
Issue Dt:
04/26/2005
Application #:
10632007
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
ARRAYS OF NONVOLATILE MEMORY CELLS WHEREIN EACH CELL HAS TWO CONDUCTIVE FLOATING GATES
42
Patent #:
Issue Dt:
05/30/2006
Application #:
10632154
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
FABRICATION OF GATE DIELECTRIC IN NONVOLATILE MEMORIES IN WHICH A MEMORY CELL HAS MULTIPLE FLOATING GATES
43
Patent #:
Issue Dt:
09/05/2006
Application #:
10632155
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
NONVOLATILE MEMORY CELLS WITH BURIED CHANNEL TRANSISTORS
44
Patent #:
Issue Dt:
10/04/2005
Application #:
10632186
Filing Dt:
07/30/2003
Publication #:
Pub Dt:
02/03/2005
Title:
NONVOLATILE MEMORY CELL WITH MULTIPLE FLOATING GATES FORMED AFTER THE SELECT GATE AND HAVING UPWARD PROTRUSIONS
45
Patent #:
Issue Dt:
12/13/2005
Application #:
10640928
Filing Dt:
08/14/2003
Publication #:
Pub Dt:
02/17/2005
Title:
ELECTRONIC MEMORY SUCH AS FLASH EPROM WITH BITWISE-ADJUSTED WRITING CURRENT OR/AND VOLTAGE
46
Patent #:
Issue Dt:
10/24/2006
Application #:
10640929
Filing Dt:
08/14/2003
Publication #:
Pub Dt:
02/17/2005
Title:
ELECTRONIC MEMORY HAVING IMPEDANCE-MATCHED SENSING
47
Patent #:
NONE
Issue Dt:
Application #:
10649099
Filing Dt:
08/26/2003
Publication #:
Pub Dt:
03/03/2005
Title:
Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask
48
Patent #:
Issue Dt:
03/08/2005
Application #:
10655705
Filing Dt:
09/05/2003
Publication #:
Pub Dt:
03/10/2005
Title:
CORNER PROTECTION TO REDUCE WRAP AROUND
49
Patent #:
Issue Dt:
04/19/2005
Application #:
10655706
Filing Dt:
09/05/2003
Publication #:
Pub Dt:
03/10/2005
Title:
CONTROL OF AIR GAP POSITION IN A DIELECTRIC LAYER
50
Patent #:
NONE
Issue Dt:
Application #:
10658934
Filing Dt:
09/09/2003
Publication #:
Pub Dt:
02/17/2005
Title:
Floating gate memory structures and fabrication methods
51
Patent #:
Issue Dt:
02/14/2006
Application #:
10677785
Filing Dt:
10/01/2003
Publication #:
Pub Dt:
04/07/2005
Title:
MULTI-TOOL, MULTI-SLURRY CHEMICAL MECHANICAL POLISHING
52
Patent #:
Issue Dt:
01/04/2005
Application #:
10678317
Filing Dt:
10/03/2003
Title:
NONVOLATILE MEMORY FABRICATION METHODS COMPRISING LATERAL RECESSING OF DIELECTRIC SIDEWALLS AT SUBSTRATE ISOLATION REGIONS
53
Patent #:
Issue Dt:
11/08/2005
Application #:
10689908
Filing Dt:
10/20/2003
Publication #:
Pub Dt:
05/06/2004
Title:
NONVOLATILE MEMORY STRUCTURES AND FABRICATION METHODS
54
Patent #:
Issue Dt:
07/10/2007
Application #:
10702527
Filing Dt:
11/05/2003
Publication #:
Pub Dt:
05/05/2005
Title:
METHOD FOR PROVIDING REPRESENTATIVE FEATURES FOR USE IN INSPECTION OF PHOTOLITHOGRAPHY MASK AND FOR USE IN INSPECTION PHOTO-LITHOGRAPHICALLY DEVELOPED AND/OR PATTERNED WAFER LAYERS, AND PRODUCTS OF SAME
55
Patent #:
Issue Dt:
10/18/2005
Application #:
10702711
Filing Dt:
11/05/2003
Publication #:
Pub Dt:
05/05/2005
Title:
FORMATION OF A DOUBLE GATE STRUCTURE
56
Patent #:
Issue Dt:
06/12/2007
Application #:
10718008
Filing Dt:
11/19/2003
Publication #:
Pub Dt:
05/19/2005
Title:
PRECISION CREATION OF INTER-GATES INSULATOR
57
Patent #:
Issue Dt:
11/20/2007
Application #:
10718320
Filing Dt:
11/19/2003
Publication #:
Pub Dt:
05/19/2005
Title:
DYNAMICALLY CONTROLLABLE REDUCTION OF VERTICAL CONTACT DIAMETER THROUGH ADJUSTMENT OF ETCH MASK STACK FOR DIELECTRIC ETCH
58
Patent #:
Issue Dt:
06/17/2008
Application #:
10732616
Filing Dt:
12/09/2003
Publication #:
Pub Dt:
06/09/2005
Title:
SUBSTRATE ISOLATION IN INTEGRATED CIRCUITS
59
Patent #:
Issue Dt:
02/21/2006
Application #:
10769025
Filing Dt:
01/30/2004
Publication #:
Pub Dt:
09/23/2004
Title:
FLOATING GATE NITRIDATION
60
Patent #:
Issue Dt:
11/27/2007
Application #:
10772520
Filing Dt:
02/04/2004
Publication #:
Pub Dt:
08/04/2005
Title:
USE OF PEDESTALS TO FABRICATE CONTACT OPENINGS
61
Patent #:
Issue Dt:
07/04/2006
Application #:
10772932
Filing Dt:
02/04/2004
Publication #:
Pub Dt:
08/04/2005
Title:
USE OF MULTIPLE ETCHING STEPS TO REDUCE LATERAL ETCH UNDERCUT
62
Patent #:
Issue Dt:
01/25/2005
Application #:
10800190
Filing Dt:
03/12/2004
Publication #:
Pub Dt:
09/09/2004
Title:
TWO STAGE ETCHING OF SILICON NITRIDE TO FORM A NITRIDE SPACER
63
Patent #:
Issue Dt:
01/18/2005
Application #:
10803599
Filing Dt:
03/17/2004
Publication #:
Pub Dt:
11/18/2004
Title:
FABRICATION OF GATE DIELECTRIC IN NONVOLATILE MEMORIES HAVING SELECT, FLOATING AND CONTROL GATES
Assignor
1
Exec Dt:
06/22/2004
Assignee
1
3F, NO. 19, LI-HSIN ROAD
SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU CITY, TAIWAN
Correspondence name and address
MACPHERSON KWOK CHEN & HEID LLP
MICHAEL SHENKER
1762 TECHNOLOGY DRIVE
STE. 226
SAN JOSE, CA 95110

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