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Patent Assignment Details

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Reel/Frame:	006136/0960			Pages:	4
		Recorded:	05/28/1992
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST.

Total properties: 13

Patent #:	5440752	Issue Dt:	08/08/1995	Application #:	07726893	Filing Dt:	07/08/1991
Title:	MICROPROCESSOR ARCHITECTURE WITH A SWITCH NETWORK FOR DATA TRANSFER BETWEEN CACHE, MEMORY PORT, AND IOU

Patent #:	5166089	Issue Dt:	11/24/1992	Application #:	07727744	Filing Dt:	07/10/1991
Title:	METHOD OF MAKING ELECTROSTACTIC DISCHARGE PROTECTION FOR SEMICONDUCTOR INPUT DEVICES

Patent #:	5261106	Issue Dt:	11/09/1993	Application #:	07805838	Filing Dt:	12/13/1991
Title:	SEMAPHORE BYPASS

Patent #:	5539911	Issue Dt:	07/23/1996	Application #:	07817810	Filing Dt:	01/08/1992
Title:	HIGH-PERFORMANCE, SUPERSCALAR-BASED COMPUTER SYSTEM WITH OUT-OF-ORDER INSTRUCTION EXECUTION

Patent #:	5345394	Issue Dt:	09/06/1994	Application #:	07833419	Filing Dt:	02/10/1992
Title:	METHOD FOR GENERATING POWER SLITS

Patent #:	5297287	Issue Dt:	03/22/1994	Application #:	07844494	Filing Dt:	03/02/1992
Title:	SYSTEM AND METHOD FOR RESETTING A MICROPROCESSOR SYSTEM

Patent #:	5828861	Issue Dt:	10/27/1998	Application #:	07846231	Filing Dt:	03/06/1992
Title:	SYSTEM AND METHOD FOR REDUCING THE CRITICAL PATH IN MEMORY CONTROL INPUT/OUTPUT CONTROL UNIT OPERATIONS

Patent #:	5398330	Issue Dt:	03/14/1995	Application #:	07846237	Filing Dt:	03/05/1992
Title:	REGISTER FILE BACKUP QUEUE

Patent #:	5438668	Issue Dt:	08/01/1995	Application #:	07857599	Filing Dt:	03/31/1992
Title:	A SYSTEM AND METHOD FOR EXTRACTION, ALIGNMENT AND DECODING OF CISC INSTRUCTIONS INTO A NANO-INSTRUCTION BUCKET FOR EXECUTION BY A RISC COMPUTER

Patent #:	5452401	Issue Dt:	09/19/1995	Application #:	07860717	Filing Dt:	03/31/1992
Title:	SELECTIVE POWER-DOWN FOR HIGH PERFORMANCE CPU/SYSTEM

Patent #:	5371684	Issue Dt:	12/06/1994	Application #:	07860718	Filing Dt:	03/31/1992
Title:	SEMICONDUCTOR FLOOR PLAN FOR A REGISTER RENAMING CIRCUIT

Patent #:	5444853	Issue Dt:	08/22/1995	Application #:	07862623	Filing Dt:	03/31/1992
Title:	A SYSTEM AND METHOD FOR TRANSFERRING DATA BETWEEN A PLURALITY OF VIRTUAL FIFOS AND A PERIPHERAL VIA A HARDWARE FIFO AND SELECTIVELY UPDATING CONTRO INFORMATION ASSOCIATED WITH THE VIRTUAL FIFOS

Patent #:	5325320	Issue Dt:	06/28/1994	Application #:	07877562	Filing Dt:	05/01/1992
Title:	AREA-EFFICIENT MULTIPLIER FOR USE IN AN INTEGRATED CIRCUIT

Assignor

Exec Dt:

05/22/1992

Assignee

4-1 NISHISHINJUKU 2-CHOME

SHINJUKI-KU TOKYO-TO, JAPAN

Correspondence name and address
	STERNE, KESSLER, GOLDSTEIN & FOX
	1225 CONNECTICUT AVE.
	WASHINGTON, DC 20036

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