Total properties:
34
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09285232
|
Filing Dt:
|
04/01/1999
|
Title:
|
BIT LINE CROSS-OVER LAYOUT ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09329975
|
Filing Dt:
|
06/10/1999
|
Title:
|
HIERARCHICAL DYNAMIC MEMORY ARRAY ARCHITECTURE USING READ AMPLIFIERS SEPARATE FROM BIT LINE SENSE AMPLIFIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09356805
|
Filing Dt:
|
07/20/1999
|
Title:
|
METHOD OF AND APPARATUS FOR SHARING REDUNDANCY CIRCUITS BETWEEN MEMORY ARRAYS WITHIN A SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09372320
|
Filing Dt:
|
08/11/1999
|
Title:
|
DYNAMIC MEMORY ARRAY HAVING WRITE DATA APPLIED TO SELECTED BIT LINE SENSE AMPLIFIERS BEFORE SENSING TO WRITE ASSOCIATED SELECTED MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09433245
|
Filing Dt:
|
11/03/1999
|
Title:
|
FLASH MEMORY ARCHITECTURE AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09451042
|
Filing Dt:
|
11/30/1999
|
Title:
|
EQUILIBRATION CIRCUIT AND METHOD USING A PULSED EQUILIBRATE SIGNAL AND A LEVEL EQUILIBRATE SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09474351
|
Filing Dt:
|
12/29/1999
|
Title:
|
PROGRAMMABLE AND ELECTRICALLY CONFIGURABLE LATCH TIMING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09499265
|
Filing Dt:
|
02/07/2000
|
Title:
|
Word line straps using two differentlayers of metal
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09502983
|
Filing Dt:
|
02/11/2000
|
Title:
|
Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09503048
|
Filing Dt:
|
02/12/2000
|
Title:
|
Merging write cycles by comparing at least a portion of the respective write cycle addresses
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09503049
|
Filing Dt:
|
02/12/2000
|
Title:
|
Intializing memory cells within a dynamic memory array prior to performing internal memory operations
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09503050
|
Filing Dt:
|
02/12/2000
|
Title:
|
Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09503108
|
Filing Dt:
|
02/11/2000
|
Title:
|
GENERATING A TAIL CURRENT FOR A DIFFERENTIAL TRANSISTOR PAIR USING A CAPACITIVE DEVICE TO PROJECT A CURRENT FLOWING THROUGH A CURRENT SOURCE DEVICE ONTO A NODE HAVING A DIFFERENT VOLTAGE THAN THE CURRENT SOURCE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09503109
|
Filing Dt:
|
02/11/2000
|
Title:
|
Dynamic memory array bit line sense amplifier enabled to drive toward, but stopped before substantially reaching, a source of voltage
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09503982
|
Filing Dt:
|
02/14/2000
|
Title:
|
Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09642253
|
Filing Dt:
|
08/17/2000
|
Title:
|
PRIORITY ENCODER WITH MULTIPLE MATCH FUNCTION FOR CONTENT ADDRESSABLE MEMORIES AND METHODS FOR IMPLEMENTING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09650971
|
Filing Dt:
|
08/29/2000
|
Title:
|
Content address memory circuit with redundant array and method for implementing the same
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2002
|
Application #:
|
09651426
|
Filing Dt:
|
08/30/2000
|
Title:
|
Content addressable memory having read/write capabilities that do not interrupt continuous search cycles
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09654316
|
Filing Dt:
|
09/01/2000
|
Title:
|
VARIABLE WIDTH CONTENT ADDRESSABLE MEMORY DEVICE FOR SEARCHING VARIABLE WIDTH DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09654319
|
Filing Dt:
|
09/01/2000
|
Title:
|
Three port content addressable memory device and methods for implementing the same
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09668431
|
Filing Dt:
|
09/22/2000
|
Title:
|
AN INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09689219
|
Filing Dt:
|
10/11/2000
|
Title:
|
METHOD FOR REDUCING THE WIDTH OF A GLOBAL DATA BUS IN A MEMORY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09757088
|
Filing Dt:
|
01/08/2001
|
Title:
|
A STRUCTURE AND METHOD OF OPERATING AN ARRAY OF NON-VOLATILE MEMORY CELL WITH SOUCE-SIDE PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
09938266
|
Filing Dt:
|
08/23/2001
|
Publication #:
|
|
Pub Dt:
|
07/11/2002
| | | | |
Title:
|
NON-VOLATILE MEMORY ARCHITECTURE AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
09999563
|
Filing Dt:
|
11/15/2001
|
Title:
|
INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
10099291
|
Filing Dt:
|
03/12/2002
|
Publication #:
|
|
Pub Dt:
|
07/11/2002
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
10100508
|
Filing Dt:
|
03/14/2002
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING AN EEPROM AND FLASH EPROM USING A MEMORY CELL WITH SOURCE-SIDE PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2009
|
Application #:
|
11085770
|
Filing Dt:
|
03/21/2005
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF AUTOMATIC INTERNAL REFRESH OF MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11208134
|
Filing Dt:
|
08/19/2005
|
Title:
|
METHODS AND CIRCUITRY FOR BUILT-IN SELF-TESTING OF CONTENT ADDRESSABLE MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
11514286
|
Filing Dt:
|
08/30/2006
|
Title:
|
METHODS AND CIRCUITRY FOR BUILT-IN SELF-TESTING OF CONTENT ADDRESSABLE MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12635543
|
Filing Dt:
|
12/10/2009
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
Title:
|
CONCURRENT MEMORY BANK ACCESS AND REFRESH RETIREMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13436381
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
CONCURRENT MEMORY BANK ACCESS AND REFRESH REQUEST QUEUING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
13857627
|
Filing Dt:
|
04/05/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
REFRESH REQUEST QUEUING CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
14830667
|
Filing Dt:
|
08/19/2015
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
REFRESH REQUEST QUEUING CIRCUITRY
|
|