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Patent Assignment Details
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Reel/Frame:046175/0969   Pages: 7
Recorded: 06/22/2018
Attorney Dkt #:LIENRELEASEQ2DRAKESALE
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 28
1
Patent #:
7067377
Issue Dt:
06/27/2006
Application #:
10812703
Filing Dt:
03/30/2004
Title:
RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
2
Patent #:
8397034
Issue Dt:
03/12/2013
Application #:
10847531
Filing Dt:
05/17/2004
Title:
MULTI-PORT ARBITRATION SYSTEM AND METHOD
3
Patent #:
7488657
Issue Dt:
02/10/2009
Application #:
11155707
Filing Dt:
06/16/2005
Publication #:
US20060286750
Pub Dt:
12/21/2006
Title:
METHOD AND SYSTEM FOR FORMING STRAIGHT WORD LINES IN A FLASH MEMORY ARRAY
4
Patent #:
7394125
Issue Dt:
07/01/2008
Application #:
11361277
Filing Dt:
02/24/2006
Title:
RECESSED CHANNEL WITH SEPARATED ONO MEMORY DEVICE
5
Patent #:
7809035
Issue Dt:
10/05/2010
Application #:
11432987
Filing Dt:
05/12/2006
Publication #:
US20070230525
Pub Dt:
10/04/2007
Title:
EYE-SAFE LASER NAVIGATION SENSOR
6
Patent #:
7742514
Issue Dt:
06/22/2010
Application #:
11591015
Filing Dt:
10/31/2006
Title:
LASER NAVIGATION SENSOR
7
Patent #:
7816697
Issue Dt:
10/19/2010
Application #:
11710034
Filing Dt:
02/23/2007
Title:
SYSTEM AND METHOD FOR MOUNTING AN OPTICAL COMPONENT TO AN INTEGRATED CIRCUIT PACKAGE
8
Patent #:
7829936
Issue Dt:
11/09/2010
Application #:
11873822
Filing Dt:
10/17/2007
Publication #:
US20090101963
Pub Dt:
04/23/2009
Title:
SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS
9
Patent #:
8987092
Issue Dt:
03/24/2015
Application #:
12110974
Filing Dt:
04/28/2008
Publication #:
US20090269916
Pub Dt:
10/29/2009
Title:
METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SEMICIRCULAR TOP SURFACES AND ROUNDED TOP CORNERS AND EDGES
10
Patent #:
7867899
Issue Dt:
01/11/2011
Application #:
12111886
Filing Dt:
04/29/2008
Publication #:
US20090268500
Pub Dt:
10/29/2009
Title:
WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE
11
Patent #:
8669597
Issue Dt:
03/11/2014
Application #:
12116200
Filing Dt:
05/06/2008
Publication #:
US20090278173
Pub Dt:
11/12/2009
Title:
MEMORY DEVICE INTERCONNECTS AND METHOD OF MANUFACTURING
12
Patent #:
7998846
Issue Dt:
08/16/2011
Application #:
12209478
Filing Dt:
09/12/2008
Publication #:
US20100065940
Pub Dt:
03/18/2010
Title:
3-D INTEGRATED CIRCUIT SYSTEM AND METHOD
13
Patent #:
7723659
Issue Dt:
05/25/2010
Application #:
12287604
Filing Dt:
10/10/2008
Title:
SYSTEM AND METHOD FOR SCREENING SEMICONDUCTOR LASERS
14
Patent #:
7851306
Issue Dt:
12/14/2010
Application #:
12327641
Filing Dt:
12/03/2008
Publication #:
US20090090953
Pub Dt:
04/09/2009
Title:
METHOD FOR FORMING A FLASH MEMORY DEVICE WITH STRAIGHT WORD LINES
15
Patent #:
7951704
Issue Dt:
05/31/2011
Application #:
12512960
Filing Dt:
07/30/2009
Publication #:
US20090289369
Pub Dt:
11/26/2009
Title:
MEMORY DEVICE PERIPHERAL INTERCONNECTS AND METHOD OF MANUFACTURING
16
Patent #:
9012333
Issue Dt:
04/21/2015
Application #:
12556199
Filing Dt:
09/09/2009
Publication #:
US20110057248
Pub Dt:
03/10/2011
Title:
VARIED SILICON RICHNESS SILICON NITRIDE FORMATION
17
Patent #:
8441041
Issue Dt:
05/14/2013
Application #:
12943679
Filing Dt:
11/10/2010
Publication #:
US20110057315
Pub Dt:
03/10/2011
Title:
MEMORY DEVICE PERIPHERAL INTERCONNECTS
18
Patent #:
9240418
Issue Dt:
01/19/2016
Application #:
12961379
Filing Dt:
12/06/2010
Publication #:
US20110095370
Pub Dt:
04/28/2011
Title:
WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE
19
Patent #:
NONE
Issue Dt:
Application #:
13183373
Filing Dt:
07/14/2011
Publication #:
US20110272775
Pub Dt:
11/10/2011
Title:
3D INTEGRATED CIRCUIT SYSTEM AND METHOD
20
Patent #:
8835277
Issue Dt:
09/16/2014
Application #:
13680726
Filing Dt:
11/19/2012
Publication #:
US20140141591
Pub Dt:
05/22/2014
Title:
Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability
21
Patent #:
8767867
Issue Dt:
07/01/2014
Application #:
13783954
Filing Dt:
03/04/2013
Title:
INTEGRATED CONTROL OF POWER SUPPLY AND POWER LINE COMMUNICATIONS
22
Patent #:
NONE
Issue Dt:
Application #:
14102446
Filing Dt:
12/10/2013
Publication #:
US20140151887
Pub Dt:
06/05/2014
Title:
Memory Device Interconnects and Method of Manufacture
23
Patent #:
NONE
Issue Dt:
Application #:
14102450
Filing Dt:
12/10/2013
Publication #:
US20140145337
Pub Dt:
05/29/2014
Title:
Memory Device Interconnects and Method of Manufacture
24
Patent #:
NONE
Issue Dt:
Application #:
14270700
Filing Dt:
05/06/2014
Publication #:
US20150255480
Pub Dt:
09/10/2015
Title:
METHOD TO IMPROVE CHARGE TRAP FLASH MEMORY TOP OXIDE QUALITY
25
Patent #:
NONE
Issue Dt:
Application #:
14486421
Filing Dt:
09/15/2014
Publication #:
US20150035044
Pub Dt:
02/05/2015
Title:
Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability
26
Patent #:
NONE
Issue Dt:
Application #:
14665311
Filing Dt:
03/23/2015
Publication #:
US20150194499
Pub Dt:
07/09/2015
Title:
VARIED SILICON RICHNESS SILICON NITRIDE FORMATION
27
Patent #:
NONE
Issue Dt:
Application #:
15239580
Filing Dt:
08/17/2016
Publication #:
US20170092577
Pub Dt:
03/30/2017
Title:
Memory Device Interconnects and Method of Manufacture
28
Patent #:
10644126
Issue Dt:
05/05/2020
Application #:
15690494
Filing Dt:
08/30/2017
Publication #:
US20180006132
Pub Dt:
01/04/2018
Title:
VARIED SILICON RICHNESS SILICON NITRIDE FORMATION
Assignor
1
MORGAN STANLEY SENIOR FUNDING INC.,
Exec Dt:
06/20/2018
Assignee
1
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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