Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 043475/0970 | |
| Pages: | 5 |
| | Recorded: | 09/03/2017 | | |
| Attorney Dkt #: | TW0027-ROBERT ROUNTREE |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
12
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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13457464
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Filing Dt:
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04/26/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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LOW NOISE MEMORY ARRAY
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13487225
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Filing Dt:
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06/03/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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LOW NOISE MEMORY ARRAY
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Patent #:
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Issue Dt:
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09/03/2013
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Application #:
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13609005
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Filing Dt:
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09/10/2012
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Publication #:
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Pub Dt:
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05/16/2013
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Title:
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POWER SUPPLY PROTECTION CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13762345
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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08/08/2013
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Title:
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PROGRAMMABLE SCR FOR ESD PROTECTION
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13763583
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Filing Dt:
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02/08/2013
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Publication #:
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Pub Dt:
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08/08/2013
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Title:
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LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13772105
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Filing Dt:
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02/20/2013
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Publication #:
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Pub Dt:
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08/22/2013
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Title:
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JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS
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Patent #:
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Issue Dt:
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03/11/2014
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Application #:
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13775672
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Filing Dt:
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02/25/2013
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Publication #:
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Pub Dt:
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09/05/2013
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Title:
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LOW VOLTAGE ANTIFUSE PROGRAMMING CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13899714
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Filing Dt:
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05/22/2013
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Publication #:
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Pub Dt:
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10/31/2013
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Title:
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LOW NOISE MEMORY ARRAY
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Patent #:
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Issue Dt:
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05/20/2014
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Application #:
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13900392
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Filing Dt:
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05/22/2013
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Publication #:
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Pub Dt:
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10/31/2013
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Title:
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LOW NOISE MEMORY ARRAY
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Patent #:
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Issue Dt:
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09/23/2014
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Application #:
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14081246
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Filing Dt:
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11/15/2013
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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14449283
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Filing Dt:
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08/01/2014
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Publication #:
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Pub Dt:
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11/20/2014
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Title:
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JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS
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Patent #:
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Issue Dt:
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05/12/2015
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Application #:
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14509963
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Filing Dt:
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10/08/2014
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Publication #:
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Pub Dt:
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01/22/2015
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Title:
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PROGRAMMABLE SCR FOR ESD PROTECTION
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Assignee
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| NO.8, LI-HSIN RD. VI, HSINCHU SCIENCE PARK, |
| HSINCHU, TAIWAN 30078 |
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Correspondence name and address
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JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE
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7F.-1, NO. 100, ROOSEVELT RD., SEC. 2,
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TAIPEI, TAIWAN
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