Patent Assignment Details
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Reel/Frame: | 005102/0980 | |
| Pages: | 2 |
| | Recorded: | 07/21/1989 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST. |
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Total properties:
1
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Patent #:
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Issue Dt:
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01/25/1994
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Application #:
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07356023
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Filing Dt:
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05/23/1989
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Title:
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METHOD AND APPARATUS FOR THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS EMPLOYING LOGIC DECOMPOSITION ALGORITHMS FOR THE TIMING OPTIMIZATION OF MULTILEVEL LOGIC
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Correspondence name and address
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BRADLEY A. PERKINS
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VLSI TECHNOLOGY, INC
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1109 MCKAY DRIVE
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SAN JOSE, CA 95131
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