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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:023731/0988   Pages: 5
Recorded: 01/06/2010
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 27
1
Patent #:
Issue Dt:
07/14/2009
Application #:
11450112
Filing Dt:
06/09/2006
Publication #:
Pub Dt:
12/13/2007
Title:
SELF ALIGNED GATE JFET STRUCTURE AND METHOD
2
Patent #:
Issue Dt:
01/05/2010
Application #:
11451886
Filing Dt:
06/12/2006
Publication #:
Pub Dt:
12/13/2007
Title:
SCALABLE PROCESS AND STRUCTURE FOR JFET FOR SMALL AND DECREASING LINE WIDTHS
3
Patent #:
Issue Dt:
09/22/2009
Application #:
11452442
Filing Dt:
06/13/2006
Publication #:
Pub Dt:
11/15/2007
Title:
CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL JFET DEVICES
4
Patent #:
Issue Dt:
12/15/2009
Application #:
11484402
Filing Dt:
07/11/2006
Publication #:
Pub Dt:
01/17/2008
Title:
OXIDE ISOLATED METAL SILICON-GATE JFET
5
Patent #:
Issue Dt:
01/12/2010
Application #:
11495908
Filing Dt:
07/28/2006
Publication #:
Pub Dt:
11/15/2007
Title:
LEVEL SHIFTING CIRCUIT HAVING JUNCTION FIELD EFFECT TRANSISTORS
6
Patent #:
Issue Dt:
07/07/2009
Application #:
11502172
Filing Dt:
08/10/2006
Publication #:
Pub Dt:
02/14/2008
Title:
JFET WITH BUILT IN BACK GATE IN EITHER SOI OR BULK SILICON
7
Patent #:
Issue Dt:
04/28/2009
Application #:
11590265
Filing Dt:
10/31/2006
Publication #:
Pub Dt:
05/01/2008
Title:
SEMICONDUCTOR DEVICE, DESIGN METHOD AND STRUCTURE
8
Patent #:
Issue Dt:
01/06/2009
Application #:
11635004
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
06/07/2007
Title:
METHOD OF PRODUCING AND OPERATING A LOW POWER JUNCTION FIELD EFFECT TRANSISTOR
9
Patent #:
Issue Dt:
04/06/2010
Application #:
11693441
Filing Dt:
03/29/2007
Publication #:
Pub Dt:
10/02/2008
Title:
SYSTEM AND METHOD FOR DETECTING MULTIPLE MATCHES
10
Patent #:
Issue Dt:
01/12/2010
Application #:
11743973
Filing Dt:
05/03/2007
Publication #:
Pub Dt:
11/06/2008
Title:
TRANSISTOR PROVIDING DIFFERENT THRESHOLD VOLTAGES AND METHOD OF FABRICATION THEREOF
11
Patent #:
Issue Dt:
04/28/2009
Application #:
11744080
Filing Dt:
05/03/2007
Publication #:
Pub Dt:
11/06/2008
Title:
JFET DEVICE WITH IMPROVED OFF-STATE LEAKAGE CURRENT AND METHOD OF FABRICATION
12
Patent #:
Issue Dt:
04/28/2009
Application #:
11744120
Filing Dt:
05/03/2007
Publication #:
Pub Dt:
11/06/2008
Title:
JFET DEVICE WITH VIRTUAL SOURCE AND DRAIN LINK REGIONS AND METHOD OF FABRICATION
13
Patent #:
Issue Dt:
11/18/2008
Application #:
11744617
Filing Dt:
05/04/2007
Publication #:
Pub Dt:
11/06/2008
Title:
METHOD FOR APPLYING A STRESS LAYER TO A SEMICONDUCTOR DEVICE AND DEVICE FORMED THEREFROM
14
Patent #:
Issue Dt:
05/12/2009
Application #:
11744660
Filing Dt:
05/04/2007
Publication #:
Pub Dt:
11/06/2008
Title:
SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF
15
Patent #:
Issue Dt:
04/06/2010
Application #:
11799572
Filing Dt:
05/01/2007
Publication #:
Pub Dt:
11/06/2008
Title:
SEMICONDUCTOR DEVICE STORAGE CELL STRUCTURE, METHOD OF OPERATION, AND METHOD OF MANUFACTURE
16
Patent #:
Issue Dt:
12/15/2009
Application #:
11804132
Filing Dt:
05/17/2007
Publication #:
Pub Dt:
11/20/2008
Title:
JUNCTION FIELD EFFECT DYNAMIC RANDOM ACCESS MEMORY CELL AND CONTENT ADDRESSABLE MEMORY CELL
17
Patent #:
Issue Dt:
03/16/2010
Application #:
11818388
Filing Dt:
06/14/2007
Publication #:
Pub Dt:
12/18/2008
Title:
SEMICONDUCTOR DEVICE INCLUDING A BIAS VOLTAGE GENERATOR
18
Patent #:
Issue Dt:
12/08/2009
Application #:
11888977
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/05/2009
Title:
SWITCHING CIRCUITS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
19
Patent #:
Issue Dt:
06/22/2010
Application #:
11958032
Filing Dt:
12/17/2007
Publication #:
Pub Dt:
06/18/2009
Title:
SWAPPED-BODY RAM ARCHITECTURE
20
Patent #:
Issue Dt:
03/30/2010
Application #:
11960452
Filing Dt:
12/19/2007
Publication #:
Pub Dt:
06/25/2009
Title:
SYSTEM AND METHOD FOR ROUTING CONNECTIONS
21
Patent #:
Issue Dt:
01/19/2010
Application #:
12033487
Filing Dt:
02/19/2008
Publication #:
Pub Dt:
08/20/2009
Title:
METHOD TO FABRICATE GATE ELECTRODES
22
Patent #:
Issue Dt:
05/04/2010
Application #:
12156565
Filing Dt:
06/02/2008
Publication #:
Pub Dt:
12/03/2009
Title:
PROGRAMMABLE SWITCH CIRCUIT AND METHOD, METHOD OF MANUFACTURE, AND DEVICES AND SYSTEMS INCLUDING THE SAME
23
Patent #:
Issue Dt:
10/20/2009
Application #:
12178291
Filing Dt:
07/23/2008
Title:
SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF
24
Patent #:
Issue Dt:
03/30/2010
Application #:
12195725
Filing Dt:
08/21/2008
Title:
LEVEL-SHIFTING CIRCUIT WITH BIPOLAR JUNCTION TRANSISTOR
25
Patent #:
Issue Dt:
03/30/2010
Application #:
12235164
Filing Dt:
09/22/2008
Publication #:
Pub Dt:
01/15/2009
Title:
SELF ALIGNED GATE JFET STRUCTURE AND METHOD
26
Patent #:
Issue Dt:
03/30/2010
Application #:
12263854
Filing Dt:
11/03/2008
Publication #:
Pub Dt:
03/05/2009
Title:
INTEGRATED CIRCUIT USING COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR AND MOS TRANSISTOR IN SILICON AND SILICON ALLOYS
27
Patent #:
Issue Dt:
01/12/2010
Application #:
12270964
Filing Dt:
11/14/2008
Publication #:
Pub Dt:
03/19/2009
Title:
JFET WITH BUILT IN BACK GATE IN EITHER SOI OR BULK SILICON
Assignor
1
Exec Dt:
12/07/2009
Assignee
1
130 D KNOWLES DRIVE
LOS GATOS, CALIFORNIA 95032
Correspondence name and address
DEBBIE KUS
130 D KNOWLES DRIVE
LOS GATOS, CA 95032

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