Patent Assignment Details
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| Reel/Frame: | 027620/0996 | |
| Pages: | 2 |
| | Recorded: | 01/30/2012 | | |
| Attorney Dkt #: | HSJ920110121US1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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13361925
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Filing Dt:
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01/30/2012
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Publication #:
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Pub Dt:
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08/01/2013
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Title:
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IMPLEMENTING ENHANCED DATA PARTIAL-ERASE FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING
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Assignee
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| LOCATELLIKADE 1, PARNASSUSTOREN |
| 1076 AZ AMSTERDAM, NETHERLANDS, NETHERLANDS |
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Correspondence name and address
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JOAN PENNINGTON
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535 N. MICHIGAN AVENUE
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UNIT 1804
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CHICAGO, IL 60611
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