Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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09/11/2018
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Application #:
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15196050
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Filing Dt:
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06/29/2016
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Publication #:
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Pub Dt:
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01/04/2018
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Inventors:
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Anand B. Arunagiri, Raj K. Gajavelly, Sujeet Kumar, Pradeep K. Nalla
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Title:
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INTEGRATED CIRCUIT DESIGN VERIFICATION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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NEW ORCHARD ROAD |
ARMONK, NEW YORK 10504 |
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IBM CORPORATION (AUS/ROC)- KEHE VLF KEVIN KEHE LLC |
700 LAVACA, STE 1401 |
AUSTIN, TX 78701 |
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