skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Total Assignments: 1
Patent #:
10114920
Issue Dt:
10/30/2018
Application #:
15197142
Filing Dt:
06/29/2016
Inventors:
UMESH GUPTA, SHASHANK TRIPATHI, NARESH KUMAR, ARVIND NEMBILI VEERAVALLI et al
Title:
METHOD AND APPARATUS FOR PERFORMING SIGN-OFF TIMING ANALYSIS OF CIRCUIT DESIGNS USING INTER-POWER DOMAIN LOGIC
Assignment: 1
Reel/Frame:
039050/0613Recorded: 06/30/2016Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
GUPTA, UMESH
Exec Dt:
06/02/2016
TRIPATHI, SHASHANK
Exec Dt:
05/30/2016
KUMAR, NARESH
Exec Dt:
05/30/2016
VEERAVALLI, ARVIND NEMBILI
Exec Dt:
06/08/2016
SETHIA, PRASHANT
Exec Dt:
06/06/2016
GOVILA, RITIKA
Exec Dt:
06/08/2016
Assignee:
CADENCE DESIGN SYSTEM
2655 SEELY AVENUE
SAN JOSE, CALIFORNIA 95134
Correspondent:
ROSENBERG, KLEIN & LEE
3458 ELLICOTT CENTER DRIVE, SUITE 101
ELLICOTT CITY, MD 21043

Search Results as of: 06/21/2024 03:08 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT