Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2019
|
Application #:
|
15443195
|
Filing Dt:
|
02/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
11/16/2017
| | | | |
|
Inventors:
|
MOO-KYUNG LEE, SUNGHOON KIM, JAEICK SON
|
|
Title:
|
METHOD FOR VERIFYING A LAYOUT DESIGNED FOR A SEMICONDUCTOR INTEGRATED CIRCUIT AND A COMPUTER SYSTEM FOR PERFORMING THE SAME
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 129, SAMSUNG-RO, YEONGTONG-GU |
| SUWON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF 16677 |
|
|
|
|
| VOLENTINE & WHITT, PLLC |
| 11951 FREEDOM DRIVE, SUITE 1300 |
| RESTON, VA 20190 |
|
|
Search Results as of:
06/27/2024 12:38 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
