Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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07/09/2019
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Application #:
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15996430
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Filing Dt:
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06/02/2018
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Publication #:
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Pub Dt:
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12/13/2018
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Inventors:
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Cheng C. Wang, Nitish U. Natu
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Title:
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Clock Distribution and Generation Architecture for Logic Tiles of an Integrated Circuit and Method of Operating Same
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Assignment:
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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2465 LATHAM STREET, SUITE 100 |
MOUNTAIN VIEW, CALIFORNIA 94040 |
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NEIL A. STEINBERG |
5335 WISCONSIN AVE., NW |
SUITE 440 |
WASHINGTON, D.C. 20015 |
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