Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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03/23/2021
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Application #:
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16731484
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Filing Dt:
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12/31/2019
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Inventors:
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Yizhou LIN, Jian TANG, Hongchang LIANG
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Title:
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METHOD TO REDUCE FULL-CHIP TIMING VIOLATION THROUGH TIME BUDGETING IN INTEGRATED CIRCUIT DESIGN
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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INDUSTRIAL INCUBATOR 3-8, NORTH 2-204 |
WEST HITECH ROAD, HUAYUAN INDUSTRIAL DISTRICT |
TIANJIN MUNICIPALITY, CHINA |
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LOEB & LOEB, LLP |
321 N. CLARK ST. |
SUITE 2300 |
CHICAGO, IL 60654 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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3072 SCOTT BLVD. |
SANTA CLARA, CALIFORNIA 95054 |
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LOEB & LOEB LLP |
321 N. CLARK STREET |
SUITE 2300 |
CHICAGO, IL 60654 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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INDUSTRIAL INCUBATOR 3-8, NORTH 2-204 WEST HITECH ROAD, |
HUAYUAN INDUSTRIAL DISTRICT |
TIANJIN, CHINA |
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LOEB & LOEB LLP |
321 N. CLARK STREET |
SUITE 2300 |
CHICAGO, IL 60654 |
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Assignment:
4
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1601 S. MOPAC EXPY, |
D300 |
AUSTIN, TEXAS 78746 |
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LOEB & LOEB LLP |
321 N. CLARK STREET |
SUITE 2300 |
CHICAGO, IL 60654 |
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09/23/2024 04:32 PM
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