Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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05/25/2021
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Application #:
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16729275
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Filing Dt:
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12/27/2019
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Inventors:
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Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania et al
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Title:
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LINEAR INPUT AND NON-LINEAR OUTPUT MAJORITY LOGIC GATE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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135 DORE STREET |
SAN FRANCISCO, CALIFORNIA 94103 |
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GREEN, HOWARD, & MUGHAL LLP |
5 CENTERPOINTE DR. |
SUITE 400 |
LAKE OSWEGO, OR 97035 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT INVENTOR PREVIOUSLY RECORDED AT REEL: 051478 FRAME: 0505. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
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135 DORE STREET |
SAN FRANCISCO, CALIFORNIA 94103 |
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GREEN, HOWARD, & MUGHAL LLP |
5 CENTERPOINTE DR. |
SUITE 400 |
LAKE OSWEGO, OR 97035 |
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Assignment:
3
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CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF INVENTOR PREVIOUSLY RECORDED AT REEL: 051723 FRAME: 0623. ASSIGNOR(S) HEREBY CONFIRMS THE INVENTORSHIP.
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180 STEUART STREET |
#19254 |
SAN FRANCISCO, CALIFORNIA 94105 |
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MUGHAL IP P.C. |
1500 NW BETHANY BLVD. |
SUITE 200 |
BEAVERTON, OR 97006 |
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06/18/2024 04:51 PM
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