Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/29/2021
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Application #:
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15263273
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Filing Dt:
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09/12/2016
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Inventors:
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Wolfgang Hokenmaier, Ryan A. Jurasek, Donald W. Labrecque
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Title:
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Flexible, Low-Latency Error Correction Architecture For Semiconductor Memory Products
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Assignment:
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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182 MAIN STREET, SUITE 304 |
BURLINGTON, VERMONT 05401 |
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MORGAN S. HELLER II |
199 MAIN STREET |
P O BOX 190 |
BURLINGTON, VT 05402-0190 |
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09/25/2024 05:44 AM
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