Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/30/2023
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Application #:
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17574722
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Filing Dt:
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01/13/2022
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Inventors:
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Mahalingam Nagarajan, Vaishnav Srinivas, Christophe Avoinne, Xavier Loic Leloup et al
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Title:
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SYSTEM FOR PROVIDING A LOW LATENCY AND FAST SWITCHED CASCADED DUAL PHASED LOCK LOOP (PLL) ARCHITECTURE FOR DIE-TO-DIE / SYSTEM-ON-CHIP (SOC) INTERFACES
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Assignment:
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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5775 MOREHOUSE DRIVE |
SAN DIEGO, CALIFORNIA 92121 |
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SMITH TEMPEL BLAHA LLC |
50 GLENLAKE PARKWAY |
SUITE 340 |
ATLANTA, GA 30328 |
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06/22/2024 10:39 AM
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