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Patent Assignment Abstract of Title

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Total Assignments: 1

Patent #:	11803685	Issue Dt:	10/31/2023	Application #:	18152268	Filing Dt:	01/10/2023
Inventors:	SHUAI ZHANG, HONGSHUANG DONG, YI CHEN, GAOQIANG DAI, CHUN SU, YU LIU, WEI CHEN, XIN WANG
Title:	Layout Design Method, Chip and Terminal of Power Device

Assignment: 1

Reel/Frame:

062325/0575

Recorded: 01/10/2023

Pages: 10

Conveyance:

ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Assignors:

SU, CHUN

Exec Dt:

01/05/2023

ZHANG, SHUAI

Exec Dt:

01/05/2023

LIU, YU

Exec Dt:

01/05/2023

DONG, HONGSHUANG

Exec Dt:

01/05/2023

CHEN, WEI

Exec Dt:

01/05/2023

CHEN, YI

Exec Dt:

01/05/2023

WANG, XIN

Exec Dt:

01/05/2023

DAI, GAOQIANG

Exec Dt:

01/05/2023

Assignee:

CHENGDU FUJIN POWER SEMICONDUCTOR TECHNOLOGY DEVELOPMENT CO., LTD

FLOOR 15, ZONE B5, AI INNOVATION CENTER 171 HELE 2ND STREET, HI-TECH ZONE

CHENGDU, SICHUAN, CHINA

Correspondent:

IPPIVOT PATENT AGENCY

4000 LEGATO ROAD

SUITE 1100

FAIRFAX, VA 22033

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