Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/20/2024
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Application #:
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17907099
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Filing Dt:
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09/23/2022
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Publication #:
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Pub Dt:
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04/06/2023
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Inventors:
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Ying LIU, Shengwen XIANG
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Title:
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SERDES MODULE CLOCK NETWORK ARCHITECTURE
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Assignment:
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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NO.15, GAOXIN S.AVE.1ST, HIGH-TECH INDUSTRIAL PARK, |
NANSHAN DISTRICT, |
SHENZHEN CITY, GUANGDONG PROVINCE,, CHINA |
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KUSHAL MALHOTRA |
399,15TH CROSS,5TH MAIN |
SECTOR-6, HSR LAYOUT |
BENGALURU, 560102 INDIA |
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09/21/2024 06:35 PM
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