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Patent Assignment Abstract of Title

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Total Assignments: 1

Patent #:	11916558	Issue Dt:	02/27/2024	Application #:	18080728	Filing Dt:	12/13/2022
Inventors:	Yong XU, Boris Dimitrov ANDREEV, Vikas MAHENDIYAN, Yuxin LI, Anand MERUVA et al
Title:	DDR PHY PARALLEL CLOCK PATHS ARCHITECTURE

Assignment: 1

Reel/Frame:

Recorded: 01/11/2023

Pages: 10

Conveyance:

ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Assignors:

Exec Dt:

01/02/2023

Exec Dt:

12/27/2022

Exec Dt:

01/03/2023

Exec Dt:

12/27/2022

Exec Dt:

01/10/2023

Exec Dt:

01/11/2023

Assignee:

5775 MOREHOUSE DRIVE

SAN DIEGO, CALIFORNIA 92121-1714

Correspondent:

LOZA & LOZA LLP

305 NORTH SECOND AVENUE #127

UPLAND, CA 91786

Search Results as of: 06/21/2024 05:53 AM

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