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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
09/22/1987
Application #:
06655473
Filing Dt:
09/27/1984
Inventors:
JAMES W. KEELEY, THOMAS F. JOYCE
Title:
MULTIPROCESSOR SHARED PIPELINE CACHE MEMORY WITH SPLIT CYCLE AND CONCURRENT UTILIZATION
Assignment: 1
Reel/Frame:
004320/0359Recorded: 09/27/1984Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST.
Assignors:
Exec Dt:
09/27/1984
Exec Dt:
09/27/1984
Assignee:
200 SMITH ST.
WALTHAM, MASSACHUSETTS 02154
Correspondent:
FAITH F. DRISCOLL
OFFICE OF GENERAL COUNSEL
HONEYWELL INFORMATION SYSTEMS INC.
333 WYMAN STREET M/S 734
WALTHAM, MA 02154
Assignment: 2
Reel/Frame:
006861/0068Recorded: 02/07/1994Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
01/26/1994
Assignee:
2200 MISSION COLLEGE BLVD.
SANTA CLARA, CALIFORNIA 95052
Correspondent:
JAMES H. SALTER
12400 WILSHIRE BLVD.
SEVENTH FLOOR
LOS ANGELES, CA 90025

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