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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
4899273
Issue Dt:
02/06/1990
Application #:
06940539
Filing Dt:
12/10/1986
Inventors:
KOICHIRO OMODA, SHUNSUKE MIYAMOTO, MASAYUKI MIYOSHI, TAKAYUKI NAKAGAWA, YOSHIO TAKAMINE et al
Title:
CIRCUIT SIMULATION METHOD WITH CLOCK EVENT SUPPRESSION FOR DEBUGGING L IS CIRCUITS
Assignment: 1
Reel/Frame:
005133/0344Recorded: 08/25/1989Pages: 1
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST.
Assignors:
OMODA, KOICHIRO
Exec Dt:
11/27/1986
MIYAMOTO, SHUNSUKE
Exec Dt:
11/27/1986
NAKAGAWA, TAKAYUKI
Exec Dt:
11/27/1986
TAKAMINE, YOSHIO
Exec Dt:
11/27/1986
NAGASHIMA, SHIGEO
Exec Dt:
11/27/1986
MIYOSHI, MASAYUKI
Exec Dt:
11/27/1986
KAZAMA, YOSHIHARU
Exec Dt:
11/27/1986
KINOSHITA, YOSHIAKI
Exec Dt:
11/27/1986
Assignee:
HITACHI, LTD.
6, KANDA SURUGADAI 4-CHOME
A CORP. OF JAPAN
CHIYODA-KU, TOKYO, JAPAN
Correspondent:
ANTONELLI, TERRY & WANDS
1919 PENNSYLVANIA AVENUE N.W. STE. 600
WASHINGTON, DC 20006

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