Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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09/03/1991
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Application #:
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07552627
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Filing Dt:
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07/16/1990
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Inventor:
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BERNARD BANCAL
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Title:
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VDMOS/LOGIC INTEGRATED CIRCUIT COMPRISING A VERTICAL DEPLETED MOS TRANSISTOR AND A ZENER DIODE AND A METHOD OF MAKING SAME
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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| 7, AVENUE GALLIENI |
| 94250 GENTILLY, FRANCE |
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| LOWE, PRICE, LE BLANC, |
| BECKER & SHUR |
| 99 CANAL CTR. PLAZA, STE. 300 |
| ALEXANDRIA, VA 22314 |
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