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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
Issue Dt:
03/10/1992
Application #:
07313180
Filing Dt:
02/21/1989
Inventors:
SUSUMU KOMORIYA, TAKAO KAWANABE, SHINYA NAKAGAWA, TAKAYOSHI OOSAKAYA, NOBUYUKI IRIKI
Title:
METHOD OF MAKING SEMICONDUCTOR INTEGRATED CIRCUIT, PATTERN DETECTING METHOD, AND SYSTEM FOR SEMICONDUCTOR ALIGNMENT AND REDUCED STEPPING EXPOSURE FOR USE IN SAME
Assignment: 1
Reel/Frame:
005887/0277Recorded: 10/25/1991Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST.
Assignors:
Exec Dt:
04/24/1989
Exec Dt:
04/24/1989
Exec Dt:
04/24/1989
Exec Dt:
04/24/1989
Exec Dt:
04/24/1989
Assignee:
TOKYO, JAPAN 100
Correspondent:
ANTONELLI, TERRY, STOUT & KRAUS
SUITE 600
1919 PENNSYLVANIA AVENUE, N.W.
WASHINGTON, DC 20006

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