Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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07/13/1993
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Application #:
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07710075
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Filing Dt:
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06/04/1991
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Inventors:
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PETER D. MAC WILLAMS, CLAIR C. WEBB, ROBERT L. FARRELL
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Title:
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A CACHE MEMORY INTEGRATED CIRCUIT FOR USE WITH A SYNCHRONOUS CENTRAL PROCESSOR BUS AND AN ASYNCHRONONOUS MEMORY BUS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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A CORPORATION OF DE |
3065 BOWERS AVE., |
SANTA CLARA, CALIFORNIA 95051 |
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BLAKELY SOKOLOFF |
TAYLOR & ZAFMAN |
1240 WILSHIRE BLVD., 7TH FL. |
LOS ANGELES, CA 90025 |
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