Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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07/20/1993
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Application #:
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07644780
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Filing Dt:
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01/23/1991
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Inventors:
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SHINICHI SHIOTSU, MASAHIRO TANAKA
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Title:
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INTEGRATED CIRCUIT WITH MEANS TO PREVENT ITS LOGIC OUTPUT CIRCUIT BREAKDOWN
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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| 1015, KAMIKODANAKA, NAKAHARA-KU, KAWASAKI-SHI |
| KANAGAWA, 211, JAPAN |
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| CHARLES M. MARMELSTEIN |
| SUITE 1000 |
| 1725 K STREET, N.W. |
| WASHINGTON, D.C. 20006 |
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