Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/17/1994
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Application #:
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07913108
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Filing Dt:
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07/14/1992
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Inventor:
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KOICHI MAEZAWA
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Title:
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SEMICONDUCTOR LOGIC CIRCUIT USING TWO N-TYPE NEGATIVE RESISTANCE DEVICES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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| 1-6, UCHISAIWAICHO 1-CHOME |
| CHIYODA-KU, TOKYO, JAPAN |
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| TOWNSEND AND TOWNSEND |
| WARREN P. KUJAWA |
| ONE MARKET PLAZA |
| SAN FRANCISCO, CA 94105 |
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Assignment:
2
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| 19-2 NISHI-SHINJUKU 3-CHOME, SHINJUK-KU |
| TOKYO, JAPAN 163-1 |
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| TOWNSEND AND TOWNSEND AND CREW LLP |
| KENNETH R. ALLEN |
| TWO EMBARCADERO CENTER 8TH FL. |
| SAN FRANCISCO, CA 94111-3834 |
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