Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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09/24/1996
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Application #:
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08219585
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Filing Dt:
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03/28/1994
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Inventor:
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MICHAEL N. MISHELOFF
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Title:
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TIMING MODEL AND CHARACTERIZATION SYSTEM FOR LOGIC SIMULATION OF INTEGRATED CIRCUITS WHICH TAKES INTO ACCOUNT PROCESS, TEMPERATURE AND POWERSUPPLY VARIATIONS
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Assignment:
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1109 MCKAY DRIVE |
LEGAL DEPARTMENT, MS/45 |
SAN JOSE, CALIFORNIA 95131 |
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WILLIAM G. BECKER, ESQUIRE |
VLSI TECHNOLOGY, INC. |
1109 MCKAY DRIVE |
LEGAL DEPARTMENT, MS-45 |
SAN JOSE, CA 95131 |
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