Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/15/1997
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Application #:
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08119671
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Filing Dt:
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09/03/1993
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Inventors:
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YOUNG-SEOK CHOI, KWANG-DONG YU, TAE-YOUNG WON
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Title:
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GATE-TO-DRAIN OVERLAPPED MOS TRANSISTOR FABRICATION PROCESS AND STRUCTURE THEREBY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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82-3, DODANG-DONG, WONMI-KU, PUCHON |
KYONGGI-DO, KOREA, REPUBLIC OF |
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VOLENTINE FRANCOS, PLLC |
ADAM C. VOLENTINE |
12200 SUNRISE VALLEY DRIVE |
SUITE 150 |
RESTON, VA 20191 |
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