Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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12/23/1997
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Application #:
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08668332
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Filing Dt:
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06/25/1996
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Inventor:
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YASUHIRO FUJII
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Title:
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SEMICONDUCTOR MEMORY WITH HIERARCHICAL BIT LINES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1 KAMIKODANAKA 4-CHOME, NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA 211, JAPAN |
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| ARMSTRONG, WESTERMN, HATTORI ET.AL |
| JAMES P. WELCH |
| 1725 K STREET, N.W. |
| STE. 1000 |
| WASHINGTON, DC 20006 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-1, NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU |
| TOKYO, JAPAN 163-0722 |
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| KRATZ, QUINTOS & HANSON, LLP |
| 1420 K STREET, N.W. |
| SUITE 400 |
| WASHINGTON, DC 20005 |
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Assignment:
3
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 2-10-23 SHIN-YOKOHAMA, KOHOKU-KU, YOKOHAMA-SHI |
| KANAGAWA 222-0033, JAPAN |
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| KRATZ, QUINTOS & HANSON, LLP |
| 1420 K STREET, N.W. |
| 4TH FLOOR |
| WASHINGTON, DC 20005 |
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