Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08806997
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Filing Dt:
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02/26/1997
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Inventors:
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STEVEN P. YOUNG, KAMAL CHAUDHARY, TREVOR J. BAUER
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Title:
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FPGA REPEATABLE INTERCONNECT STRUCTURE WITH HIERARCHICAL INTERCONNECT LINES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2100 LOGIC DRIVE |
| SAN JOSE, CALIFORNIA 95124 |
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| EDEL M. YOUNG |
| 2100 LOGIC DRIVE |
| SAN JOSE, CA 95124 |
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