Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09081029
|
Filing Dt:
|
05/19/1998
|
|
Inventor:
|
HISANORI SATO
|
|
Title:
|
LOGIC SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE HAVING EMBEDDED DYNAMIC RANDOM-ACCESS MEMORY
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| CHIYODA-KU |
| 2-3, MARUNOUCHI 2-CHOME |
| TOKYO 100, JAPAN |
|
|
|
|
| LEYDIG, VOIT & MAYER |
| JEFFREY A. WYAND |
| 700 THIRTEENTH STREET, N.W. SUITE 300 |
| WASHINGTON, DC 20005 |
|
|
Search Results as of:
06/07/2024 09:01 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
