Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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09073928
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Filing Dt:
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05/07/1998
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Inventors:
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TAKAAKI SUZUKI, SHINYA FUJIOKA, YASUHARU SATO
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Title:
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BIT LINE RESET CIRCUIT OF MEMORY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NAKAHARA-KU, KAWASAKI-SHI |
| 1-1, KAMIKODANAKA 4-CHOME |
| KANAGAWA 211-8588, JAPAN |
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| NIKAIDO, MARMELSTEIN, MURRAY & ORAM LLP |
| CHARLES M. MARMELSTEIN |
| METROPOLITAN SQUARE, 655 15TH ST., N.W. |
| SUITE 330 G STREET LOBBY |
| WASHINGTON, D.C. 20005-5701 |
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