Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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09268557
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Filing Dt:
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03/15/1999
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Inventors:
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WENPIN LU, YING-CHE LO, MING-JYE CHIOU, MAM TSUNG WANG
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Title:
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DEVICE AND METHOD FOR SUPPRESSING BIT LINE COLUMN LEAKAGE DURING ERASE VERIFICATION OF A MEMORY CELL
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| SCIENCE-BASED INDUSTRIAL PARK |
| NO. 3 CREATION ROAD 3RD |
| HSINCHU, TAIWAN R.O.C |
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| HAYNES & BEFFEL LLP |
| MARK A. HAYNES |
| P.O. BOX 366 |
| HALF MOON BAY, CA 94019 |
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