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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
05/01/2001
Application #:
09301220
Filing Dt:
04/29/1999
Inventor:
BING-YUE TSUI
Title:
METHOD FOR MAKING STACKED AND BORDERLESS VIA STRUCTURES ON SEMICONDUCTOR SUBSTRATES FOR INTEGRATED CIRCUITS
Assignment: 1
Reel/Frame:
009953/0579Recorded: 04/29/1999Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/13/1999
Assignee:
CHUTUNG, HSINCHU
195 SEC. 4, CHUNG HSING RD.
HSINCHU, TAIWAN R.O.C
Correspondent:
GEORGE O. SAILE
20 MCINTOSH DRIVE
POUGHKEEPSIE, NY 12603
Assignment: 2
Reel/Frame:
022856/0519Recorded: 06/23/2009Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/19/2009
Assignee:
NO. 1, DUSING RD. 1ST
SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU, TAIWAN 300, R.O.C.
Correspondent:
DANIEL R. MCCLURE
600 GALLERIA PARKWAY, S.E.
SUITE 1500
ATLANTA, GA 30339-5994

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