Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09396520
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Filing Dt:
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09/15/1999
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Inventors:
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JUN-LIN TSAZ, RUEY-HSIN LIU, JYH-MIN JIANG, JEI-FENG HWANG
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Title:
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METHOD OF FABRICATING A HIGH VOLTAGE TRANSISTOR USING P+ BURIED LAYER
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| SCIENCE-BASED INDUSTRIAL PARK |
| 121 PARK AVE. 3 |
| HSIN-CHU, TAIWAN R.O.C |
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| GEORGE O. SAILE |
| 20 MCINTOSH DRIVE |
| POUGHKEEPSIE, NY 12603 |
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