Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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01/15/2002
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Application #:
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09595143
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Filing Dt:
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06/16/2000
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Inventors:
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KIM CARVER HARDEE, JOHN D. HEIGHTLEY, LAWRENCE LEE ALDRICH
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Title:
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Architecture for high speed memory circuit having a relatively large number of internal data lines
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4815 LIST DRIVE, SUITE 109 |
| COLORADO SPRINGS, COLORADO 80919 |
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| 6-7-35 KITA-SHINAGAWA SHINAGAWA-KU |
| TOKYO, JAPAN 141-0 |
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| COOK, ALEX ET AL |
| MICHAEL J MCGEE |
| 200 W. ADAMS |
| CHICAGO, IL 60606 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| SUITE 109 |
| 4815 LIST DRIVE |
| COLORADO SPRINGS, COLORADO 80919 |
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| SHINAGAWA-KU |
| 6-7-35 KITA-SHINAGAWA |
| TOKYO 141-0001, JAPAN |
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| COOK, ALEX, MCFARRON, ETAL. |
| MICHAEL J. MCGEE |
| 200 W. ADAMS |
| CHICAGO, IL 60606 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-7-1 KONAN, MINATO-KU |
| TOKYO, JAPAN 108-0075 |
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| DANIEL M. GURFINKEL |
| 120 SOUTH LASALLE STREET, SUITE 1400 |
| CHICAGO, IL 60603 |
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