Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09651938
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Filing Dt:
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08/31/2000
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Inventor:
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Kim Carver Hardee
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Title:
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DATA BUS ARCHITECTURE FOR INTEGRATED CIRCUIT DEVICES HAVING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH A LARGE ASPECT RATIO PROVIDING REDUCED CAPACITANCE AND POWER REQUIREMENTS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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SUITE 109 |
4815 LIST DRIVE |
COLORADO SPRINGS, COLORADO 80919 |
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SHINAGAWA-KU |
6-7-35 KITA-SHINAGAWA |
TOKYO, JAPAN 141-0 |
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HOGAN & HARTSON LLP |
WILLIAM J. KUBIDA, ESQ. |
1200 17TH STREET |
SUITE 1500 |
DENVER, CO 80202 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1-7-1 KONAN, MINATO-KU |
TOKYO, JAPAN 108-0075 |
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DANIEL M. GURFINKEL |
120 SOUTH LASALLE STREET, SUITE 1400 |
CHICAGO, IL 60603 |
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