skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Total Assignments: 2
Patent #:
Issue Dt:
10/01/2002
Application #:
09651938
Filing Dt:
08/31/2000
Inventor:
Kim Carver Hardee
Title:
DATA BUS ARCHITECTURE FOR INTEGRATED CIRCUIT DEVICES HAVING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH A LARGE ASPECT RATIO PROVIDING REDUCED CAPACITANCE AND POWER REQUIREMENTS
Assignment: 1
Reel/Frame:
011070/0377Recorded: 08/31/2000Pages: 5
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
08/31/2000
Assignees:
SUITE 109
4815 LIST DRIVE
COLORADO SPRINGS, COLORADO 80919
SHINAGAWA-KU
6-7-35 KITA-SHINAGAWA
TOKYO, JAPAN 141-0
Correspondent:
HOGAN & HARTSON LLP
WILLIAM J. KUBIDA, ESQ.
1200 17TH STREET
SUITE 1500
DENVER, CO 80202
Assignment: 2
Reel/Frame:
030967/0231Recorded: 08/08/2013Pages: 5
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
01/28/2010
Assignee:
1-7-1 KONAN, MINATO-KU
TOKYO, JAPAN 108-0075
Correspondent:
DANIEL M. GURFINKEL
120 SOUTH LASALLE STREET, SUITE 1400
CHICAGO, IL 60603

Search Results as of: 05/14/2024 04:39 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT