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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
10/15/2002
Application #:
09654810
Filing Dt:
09/05/2000
Inventors:
Chyh-Yih Chang, Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng
Title:
STRUCTURE AND FABRICATION METHOD USING LATCH-UP IMPLANTATION FOR IMPROVING LATCH-UP IMMUNITY IN CMOS FABRICATION PROCESS
Assignment: 1
Reel/Frame:
011090/0169Recorded: 09/05/2000Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
07/17/2000
Exec Dt:
07/17/2000
Exec Dt:
07/17/2000
Exec Dt:
07/17/2000
Assignee:
NO. 195, SEC, 4 CHUNG-HSING RD.
CHUTUNG, HSINCHU, TAIWAN R.O.C
Correspondent:
J.C. PATENTS, INC.
JIAWEI HUANG
1340 REYNOLDS AVENUE, SUITE 114
IRVINE, CALIFORNIA 92614
Assignment: 2
Reel/Frame:
018498/0272Recorded: 11/03/2006Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
06/10/2006
Assignee:
10TH FL.-1A, NO., 207, DUNHUA N. ROAD
TAIPEI CITY 105, TAIWAN R.O.C.
Correspondent:
TROXELL LAW OFFICE PLLC
5205 LEESBURG PIKE, SUITE 1404
FALLS CHURCH, VA 22041

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