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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
6544824
Issue Dt:
04/08/2003
Application #:
10038390
Filing Dt:
01/03/2002
Inventors:
Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek et al
Title:
METHOD TO FORM A VERTICAL TRANSISTOR BY FIRST FORMING A GATE/SPACER STACK, THEN USING SELECTIVE EPITAXY TO FORM SOURCE, DRAIN AND CHANNEL
Assignment: 1
Reel/Frame:
012509/0033Recorded: 01/03/2002Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
PRADEEP, YELEHANKA RAMACHANDRAMURTHY
Exec Dt:
10/26/2001
ZHENG, JIA ZHEN
Exec Dt:
10/26/2001
CHAN, LAP
Exec Dt:
10/26/2001
QUEK, ELGIN
Exec Dt:
10/26/2001
SUNDARESAN, RAVI
Exec Dt:
10/26/2001
PAN, YANG
Exec Dt:
10/26/2001
MENG, JAMES LEE YONG
Exec Dt:
10/26/2001
LEUNG, YING KEUNG
Exec Dt:
10/26/2001
Assignee:
CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
STREET 2
60 WOODLANDS INDUSTRIAL PARK D
SINGAPORE 738406, SINGAPORE
Correspondent:
GEORGE O. SAILE
20 MCINTOSH DRIVE
POUGHKEEPSIE, NEW YORK 12603
Assignment: 2
Reel/Frame:
013091/0156Recorded: 07/11/2002Pages: 8
Conveyance:
RE-RECORD TO CORRECT THE NAMES OF THE SEVENTH AND EIGHT INVENTORS ON REEL 012509 FRAME 0033. ASSIGNORS CONFIRM THE ASSIGNMENT OF THE ENTIRE INTEREST.
Assignors:
PRADEEP, YELEHANKA RAMACHANDRAMURTHY
Exec Dt:
10/26/2001
ZHENG, JIA ZHEN
Exec Dt:
10/26/2001
CHAN, LAP
Exec Dt:
10/26/2001
QUEK, ELGIN
Exec Dt:
10/26/2001
SUNDARESAN, RAVI
Exec Dt:
10/26/2001
PAN, YANG
Exec Dt:
10/26/2001
LEE, JAMES YONG MENG
Exec Dt:
10/26/2001
KEUNG, YING LEUNG
Exec Dt:
10/26/2001
Assignee:
CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
60 WOODLANDS INDUSTRIAL PARK D STREET 2
SINGAPORE, SINGAPORE 73840
Correspondent:
GEORGE O. SAILE
20 MCINTOSH DRIVE
POUGHKEEPSIE, NY 12603

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