Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10273001
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Filing Dt:
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10/18/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Inventors:
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Atsushi Narazaki, Katsumi Uryuu
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Title:
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INSULATED GATE SEMICONDUCTOR DEVICE HAVING FIRST TRENCH AND SECOND TRENCH CONNECTED TO THE SAME
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| 1 MIZUHARA 4-CHOME, ITAMI-SHI |
| HYOGO 664-0005, JAPAN |
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| OBLON, SPIVAK, MCCLELLAND & ET AL. |
| MARVIN J. SPIVAK |
| 1755 JEFFERSON DAVIS HIGHWAY |
| FOURTH FLOOR |
| ARLINGTON, VIRGINIA 22202 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT TO CORRECT THE 2ND ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL 013405 FRAME 0644
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| 1 MIZUHARA 4-CHOME, ITAMI-SHI |
| HYOGO 664-0005, JAPAN |
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| OBLON, SPIVAK, MCCLELLAND, MAIER & NEUST |
| 1940 DUKE STREET |
| ALEXANDRIA, VA 22314 |
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