Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
09630905
|
Filing Dt:
|
08/02/2000
|
|
Inventors:
|
Shing-Wu Tung, Chun-Yao Wang, Jing-Yang Jou
|
|
Title:
|
BUILT-IN SELF VERIFICATION CIRCUIT FOR SYSTEM CHIP DESIGN
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| NO. 195, SEC. 4, CHUNG-HSING RD. |
| CHUTUNG, HSINCHU, TAIWAN R.O.C |
|
|
|
|
| J.C. PATENTS, INC. |
| JIAWEI HUANG |
| 1340 REYNOLDS AVENUE, SUITE 114 |
| IRVINE, CALIFORNIA 92614 |
|
|
Search Results as of:
05/13/2024 07:57 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
