Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10062121
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Filing Dt:
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01/31/2002
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Inventors:
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Rob A. Rutenbar, Donald B. Reaves, Elias L. Fallon
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Title:
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METHOD OF CREATING CONFORMAL OUTLINES FOR USE IN TRANSISTOR LEVEL SEMICONDUCTOR LAYOUTS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 583 EPSILON DRIVE |
| PITTSBURGH, PENNSYLVANIA 15238 |
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| WEBB ZIESENHEIM LOGSDON, ET AL. |
| WILLIAM H. LOGSDON |
| 700 KOPPERS BUILDING |
| 436 SEVENTH AVENUE |
| PITTSBURGH, PA 15219-1818 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2655 SEELY AVENUE, BUILDING 5 |
| SAN JOSE, CALIFORNIA 95134 |
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| MORRISON & FOERSTER LLP |
| ROBERT E. SCHEID |
| 425 MARKET STREET |
| SAN FRANCISCO, CA 94105 |
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