Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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09765958
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Filing Dt:
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01/18/2001
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Publication #:
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Pub Dt:
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04/04/2002
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Inventors:
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Bulent Dervisoglu, Laurence H. Cooke
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Title:
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HIERARCHICAL TEST CIRCUIT STRUCTURE FOR CHIPS WITH MULTIPLE CIRCUIT BLOCKS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2655 SEELY AVENUE |
| SAN JOSE, CALIFORNIA 95134 |
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| LYON & LYON, LLP |
| PETER C. MEI |
| 633 WEST FIFTH STREET, SUITE 4700 |
| LOS ANGELES, CA 90071-2066 |
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