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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
7093156
Issue Dt:
08/15/2006
Application #:
10144020
Filing Dt:
05/13/2002
Inventors:
Alex Shubat, Randall Lee Reichenbach
Title:
EMBEDDED TEST AND REPAIR SCHEME AND INTERFACE FOR COMPILING A MEMORY ASSEMBLY WITH REDUNDANCY IMPLEMENTATION
Assignment: 1
Reel/Frame:
012899/0758Recorded: 05/13/2002Pages: 5
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
SHUBAT, ALEX
Exec Dt:
05/08/2002
REICHENBACH, RANDALL LEE
Exec Dt:
05/08/2002
Assignee:
VIRAGE LOGIC CORP.
46501 LANDING PARKWAY
FREMONT, CALIFORNIA 94538
Correspondent:
DANAMRAJ & YOUST PC
SHREEN K. DANAMRAJ
12900 PRESTON ROAD
SUITE 1200, LB-15
DALLAS, TEXAS 75230-1328
Assignment: 2
Reel/Frame:
025105/0907Recorded: 10/08/2010Pages: 57
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
VIRAGE LOGIC CORPORATION
Exec Dt:
09/02/2010
VL C.V.
Exec Dt:
09/02/2010
ARC CORES LIMITED
Exec Dt:
09/02/2010
ARC INTERNATIONAL I.P., INC.
Exec Dt:
09/02/2010
ARC INTERNATIONAL INTELLECTUAL PROPERTY, INC.
Exec Dt:
09/02/2010
ARC INTERNATIONAL LIMITED, FORMERLY ARC INTERNATIONAL PLC
Exec Dt:
09/02/2010
ARC INTERNATIONAL (UK) LIMITED
Exec Dt:
09/02/2010
Assignee:
SYNOPSYS, INC.
700 EAST MIDDLEFIELD ROAD
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondent:
FENWICK & WEST LLP
801 CALIFORNIA ST
ATTN MICHAEL W. FARN
MOUNTAIN VIEW, CA 94041

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