Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10415733
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Filing Dt:
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10/14/2003
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Publication #:
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Pub Dt:
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03/25/2004
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Inventors:
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Masamichi Inenaga, Yuji Arinaga, Shinichi Katsuda, Takayuki Imanaka
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Title:
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TECHNIQUES FOR WAFER PREALIGNMENT AND SENSING EDGE POSITIONS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-1, KUROSAKI-SHIROISHI |
| YAHATANISHI-KU, KITAKYUSHU-SHI |
| FUKUOKA 806-0004, JAPAN |
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| SUGHRUE MION, PLLC |
| 2100 PENNSYLVANIA AVENUE, N.W. |
| SUITE 800 |
| WASHINGTON, DC 20037 |
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