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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
7191373
Issue Dt:
03/13/2007
Application #:
10086214
Filing Dt:
02/27/2002
Publication #:
20020138801
Pub Dt:
09/26/2002
Inventors:
Laung-Terng Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee et al
Title:
METHOD AND APPARATUS FOR DIAGNOSING FAILURES IN AN INTEGRATED CIRCUIT USING DESIGN-FOR-DEBUG (DFD) TECHNIQUES
Assignment: 1
Reel/Frame:
012939/0774Recorded: 05/24/2002Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
WANG, LAUNG-TERNG (L.-T.)
Exec Dt:
04/23/2002
CHANG, MING-TUNG
Exec Dt:
04/18/2002
LIN, SHYH-HORNG
Exec Dt:
04/18/2002
CHAO, HAO-JAN
Exec Dt:
04/18/2002
LEE, JAEHEE
Exec Dt:
04/23/2002
WANG, HSIN-PO
Exec Dt:
04/22/2002
WEN, XIAOQING
Exec Dt:
04/23/2002
HSU, PO-CHING
Exec Dt:
04/22/2002
KAO, SHIH-CHIA
Exec Dt:
04/22/2002
LIN, MENG-CHYI
Exec Dt:
04/22/2002
TSAI, SEN-WEI
Exec Dt:
04/22/2002
HSU, CHI-CHAN
Exec Dt:
04/18/2002
Assignee:
SYNTEST TECHNOLOGIES, INC.
SUITE 101
505 S. PASTORIA AVENUE
SUNNYVALE, CALIFORNIA 94086
Correspondent:
LAW FIRM OF JIM ZEGEER
JIM ZEGEER
801 N. PITT STREET
#108
ALEXANDRIA, VA 22314

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