Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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11121083
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Filing Dt:
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05/04/2005
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Publication #:
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Pub Dt:
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11/10/2005
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Inventor:
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Takafumi Nakashiba
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Title:
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METHOD FOR GENERATING TIMING CONSTRAINTS OF LOGIC CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1006, OAZA KADOMA |
KADOMA-SHI, OSAKA 571-8501, JAPAN |
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MCDERMOTT WILL & EMERY LLP |
600 13TH STREET, N.W. |
WASHINGTON, DC 20005-3096 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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10-23, SHINYOKOHAMA 2-CHOME, KOHOKU-KU, YOKOHAMA-SHI |
KANAGAWA, JAPAN 2220033 |
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PANASONIC CORPORATION |
2-1-61, SHIROMI, CHUO-KU |
7F OBP PANASONIC TOWER |
OSAKA, 540-6207 JAPAN |
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