Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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10878229
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Filing Dt:
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06/29/2004
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Publication #:
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Pub Dt:
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01/06/2005
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Inventors:
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Mitsuhiro Koga, Hiroshi Shinya
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ERROR CHECKING AND CORRECTING METHOD THEREOF
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, SHIBAURA 1-CHOME, MINATO-KU |
| TOKYO 105-8001, JAPAN |
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| FINNEGAN, HENDERSON, FARABOW, GARRETT & |
| & DUNNER, L.L.P. |
| MR. ERNEST F. CHAPMAN |
| 1300 I STREET, N.W. |
| WASHINGTON, DC 20001-4413 |
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